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BR34E02FVT-W, BR34E02NUX-W
Technical Note
○ WRITE PROTECT PIN(WP)
When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level),
it is enable to write 256 words (all address).
If permanent protection is done by Write Protect command, lower half area (00 ～ 7Fh address) is inhibited writing
regardless of WP pin state.
WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use.
○ Confirm Write Protect Resistor by ACK
According to state of Write Protect Resistor, ACK is as follows.
State of Write
Protect Registor
WP Input Input Command ACK
Address
ACK
Data
ACK
Write
Cycle(tWR)
(00 ～ 7Fh)
In case,
protect by PSWP
-
PSWP, SWP, CWP No ACK
Page or Byte Write
ACK
-
WA7 ～ WA0
No ACK
ACK
No ACK No
D7 ～ D0 No ACK No
SWP No ACK
CWP ACK
-
-
No ACK
ACK
-
-
No ACK
ACK
No
Yes
0
PSWP ACK
-
ACK
-
ACK
Yes
(00 ～ 7Fh)
In case,
protect by SWP
1
Page or Byte Write
ACK
SWP No ACK
CSP ACK
PSWP ACK
Page or Byte Write ACK
WA7 ～ WA0
-
-
-
WA7 ～ WA0
ACK D7 ～ D0 No ACK
No ACK - No ACK
ACK - No ACK
ACK - No ACK
ACK D7 ～ D0 No ACK
No
No
No
No
No
In case,
Not protect
0
1
PSWP, SWP, CWP ACK
Page or Byte Write ACK
PSWP, SWP, CWP ACK
Page or Byte Write ACK
-
WA7 ～ WA0
-
WA7 ～ WA0
ACK - ACK
ACK D7 ～ D0 ACK
ACK - No ACK
ACK D7 ～ D0 No ACK
Yes
Yes
No
No
*- is Don’t Care
State of Write Protect Registor
In case, protect by PSWP
In case, protect by SWP
In case, Not protect
Command
PSWP, SWP, CWP
SWP
CWP
PSWP
PSWP, SWP, CWP
ACK
No ACK
No ACK
ACK
ACK
ACK
Address
-
-
-
-
-
ACK
No ACK
No ACK
No ACK
No ACK
No ACK
Data
-
-
-
-
-
ACK
No ACK
No ACK
No ACK
No ACK
No ACK
○ Write Cycle
During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte. In
the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that can
be written at one time is 16 bytes.
S
W
T
A
R
I
S
T
R
T
SLAVE
ADDRESS
T
E
WORD
ADDRESS
DATA
O
P
SDA
LINE
1 0 1 0 A2 A1 A0
WA
7
WA
0
D7
D0
R A
A
A
/
C
C
C
S
W
W K
K
Fig.33 Byte Write Cycle Timing
K
T
A
R
I
S
T
R
T
S LA V E
ADDRESS
T
E
W ORD
A D D R E S S (n )
D A TA (n)
D A TA (n + 1 5)
O
P
SDA
L IN E
1 0 1 0 A 2 A 1 A 0
WA
7
WA
0
D7
D0
D0
R A
/ C
W K
A
C
K
A
C
K
A
C
K
Fig.34 Page Write Cycle Timing
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
8/18
2009.09 - Rev.B
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